The present invention relates to semiconductor memory devices, and more particularly, to a method and apparatus for improved memory self-timing.
Memory devices typically include a memory core having an array of memory cells for storage and retrieval of data. The array of memory cells are arranged in rows and columns. The rows of memory cells are coupled through word lines and the columns of memory cells are coupled through bit lines. Each column can have a single bit line (for single-ended memory cells) or a complementary bit line pair (for dual-ended memory cells). Although many architectures are possible, a row or word line decoder including a plurality of word line drivers and a column decoder are provided for decoding an address for accessing a particular location of the memory array. Sense amplifiers are enabled to sense the data from the memory cells in the array on the bit lines or bit line pairs. The sense amplifiers output the data to latches which latch the data.
The latching of the data must be delayed for a period of time after the access cycle commences to ensure that the data from the sense amplifiers is valid. Part of the delay is the result of RC delay in the word lines due to the capacitance of the memory cells that are electrically coupled to the word lines in each row. Similarly, RC delay is also produced in the columns of the memory core due to the capacitance of the memory cells that are electrically coupled to the bit lines in each column. Thus, each access to a particular memory cell includes a delay between the assertion of the word line corresponding to the memory cell and the activation of the memory cell, and a delay between the activation of the memory cell and the discharge of the bit line or bit line pair to which it is connected. The data from the sense amplifiers is not valid until after these delays have expired Consequently, it is desirable to provide timing control to prevent the latching of the data from the sense amplifiers prior to the expiration of an appropriate delay, generally a worst-case delay, to ensure that the data being latched is valid. The worst-case RC delay is generally associated with a worst-case memory cell that is located furthest from a given word line driver and a given sense amplifier.
Additionally, the sense amplifiers consume an appreciable amount of power while activated. As result, it is also desirable to provide timing control that deactivates (shuts down) the data sense amplifiers as soon as possible after the data has been latched.
Various methods are known for providing the desired timing control for the data sense amplifiers, including self-timing circuitry. Self-timing circuitry is used in conventional memory designs to provide a timing control signal that indicates when data from the sense amplifiers of the memory core should be latched and when the sense amplifiers can be deactivated. The self-timing circuitry is intended to provide a delay that at least meets the worst-case RC delay of the memory core.
One type of self-timing architecture involves simulating the worst-case RC delay by reproducing the longest path of the memory core. Here, the self-timing circuit generally includes a column Of dummy bit cells coupled to a dummy sense amplifier through a dummy bit line pair (or a single bit line for single-ended bit cells). The column of dummy bit cells includes a worst-case dummy bit cell that is coupled to a dummy word line driver of the word line decoder of the memory core. The remaining dummy bit cells are not coupled to a word line and do not assert data on the dummy bit line pair. Instead, the remaining dummy bit cells are used to simulate the RC delay that exists in a column of the memory core. Similarly, a row of dummy bitcells can be coupled to the dummy word line to provide additional RC delay that relates to the RC delay produced by a row of the memory core. The worst-case dummy bit cell is preferably positioned similarly to the worst-case memory cell of the memory core.
The word line decoder of the memory device typically includes a dummy word line driver, which receives a word line enable signal from control logic during every access cycle, and correspondingly asserts the dummy word line. The assertion of the dummy word line causes a memory read access to occur in the self-timing circuitry simultaneously with each access of the memory core. The worst-case dummy bit cell is configured to assert predetermined complementary logic levels on the dummy bit line pair. The dummy sense amplifier senses the predetermined complementary logic levels asserted by the worst-case dummy bit cell and responds by asserting a timing control signal. Control logic detects the assertion of the timing control signal and responds by asserting latch signals to the latches of the memory core, which latch the output data from the sense amplifiers. Additionally, the control logic, in response to the timing control signal, can deassert word line enable and sense enable signals to shut down the word line decoder and the sense amplifiers, respectively, to prevent further power drain in the memory array. In this manner, the output data is latched and the sense amplifiers are shut down as soon as possible to conserve energy, but not prior to the worst-case RC delay in an effort to ensure that only valid data is latched. As a result, a worst-case RC delay associated with the RC delays corresponding to the rows and columns of the memory core can be taken into account with the above-described self-timing scheme.
Unfortunately, the RC delays of the memory core are not the only sources of delay that exist in a conventional memory device. Current leaking from pass gates of the memory core cells to the bit line or bit line pair can hinder the driving of the bit line or bit line pair to the state or logic level that represents the data of the memory cell being accessed, thereby introducing additional delay. This delay is defined as leakage current delay. This leakage current delay can result in a greater worst-case delay for the memory array than the worst-case RC delay estimated by conventional self-timing schemes. As a result, conventional self-timing schemes can result in an underestimation of the worst-case delay for a given memory core. Consequently, invalid data can be latched and sense amplifiers can be shut down prematurely due to the underestimation of the worst-case delay.